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CY7C1011DV33
2-Mbit (128K x 16)Static RAM
Features
* Pin-and function-compatible with CY7C1011CV33 * High speed -- tAA = 10 ns * Low active power -- ICC = 90 mA @ 10 ns (Industrial) * Low CMOS standby power * * * * * -- ISB2 = 10 mA Data Retention at 2.0 V Automatic power-down when deselected Independent control of upper and lower bits Easy memory expansion with CE and OE features Available in Lead-Free 44-pin TSOP II, and 48-ball VFBGA
Functional Description
The CY7C1011DV33 is a high-performance CMOS Static RAM organized as 128K words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1011DV33 is available in standard Lead-Free 44-pin TSOP II with center power and ground pinout, as well as 48-ball fine-pitch ball grid array (VFBGA) packages .
Logic Block Diagram
INPUT BUFFER
Pin Configuration
TSOP II Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A0 A1 A2 A3 A4 A5 A6 A7 A8
I/O0-I/O7 I/O8-I/O15
128K X 16
COLUMN DECODER
BHE WE CE OE BLE
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
ROW DECODER
Note 1. For guidelines on SRAM system design, please refer to the "System Design Guidelines" Cypress application note, available on the internet at www.cypress.com
Cypress Semiconductor Corporation Document #: 38-05609 Rev. *C
A9 A10 A 11 A 12 A 13 A14 A15 A16
SENSE AMPS
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised July 14, 2006
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CY7C1011DV33
Selection Guide
Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -10 10 90 10 Unit ns mA mA
Pin Configurations
48-Ball VFBGA (Top View)
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 3 A0 A3 A5 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H
I/O11 NC I/O12 I/O13 NC A8 NC A14 A12 A9
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CY7C1011DV33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[3] .... -0.3V to +4.6V DC Voltage Applied to Outputs in High-Z State[3] .....................................-0.3V to VCC +0.3V DC Input Voltage[3] ..................................-0.3V to VCC +0.3V
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 3.3V 0.3V
DC Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz ISB1 Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 -10 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 90 80 70 60 20 mA Max. Unit V V V V A A mA
ISB2
10
mA
Capacitance[3]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF
Notes 2. VIL (min.) = -2.0V and VIH(max) = VCC +2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters.
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CY7C1011DV33
Thermal Resistance[3]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board TSOP II 50.66 17.17 VFBGA 27.89 14.74 Unit C/W C/W
AC Test Loads and Waveforms[4]
Z = 50 OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V Rise Time: 1 V/ns (a) High-Z characteristics: R 317 3.3V OUTPUT 5 pF R2 351 (c) (b) Fall Time: 1 V/ns 3.0V 90% ALL INPUT PULSES 90% 10% 10%
30 pF*
GND
AC Switching Characteristics Over the Operating Range[5]
Parameter Read Cycle tpower[6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z[7, 8] CE LOW to Low-Z[8] CE HIGH to High-Z[7, 8] 0 10 CE LOW to Power-up CE HIGH to Power-down 3 5 0 5 3 10 5 100 10 10 s ns ns ns ns ns ns ns ns ns ns ns Description -10 Min. Max. Unit
Notes 4. AC characteristics (except High-Z) are tested using the load conditions shown in (a). High-Z characteristics are tested for all speeds using the test load shown in (c). 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed. 7. tHZOE, tHZCE, tHZBE and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given device.
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CY7C1011DV33
AC Switching Characteristics Over the Operating Range[5] (continued)
Parameter tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW
[9, 10]
Description Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[8] WE LOW to High-Z[7, 8] Byte Enable to End of Write
-10 Min. 0 6 10 7 7 0 0 7 5 0 3 5 7 Max. 5
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Retention Characteristics Over the Operating Range
Parameter VDR ICCDR tCDR
[3]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions[12]
Min. 2.0
Max. 10
Unit V mA ns ns
tR[13]
VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V
0 tRC
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
Notes 9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. No input may exceed VCC + 0.3V. 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s
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CY7C1011DV33
Switching Waveforms
Read Cycle No. 1[11, 14]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2(OE Controlled)[14, 15]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE
HIGH IMPEDANCE
DATA OUT
Notes 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW.
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CY7C1011DV33
Switching Waveforms (continued)
Write Cycle No. 1(CE Controlled)[16, 17]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
Notes 16. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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CY7C1011DV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE HIGH During Write)[16, 17]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
OE
BHE, BLE t DATA I/O NOTE 18 t
HZOE SD
tHD
DATAIN VALID
Write Cycle No. 4 (WE Controlled, OE LOW)
BHE, BLE ADDRESS
tWC
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O NOTE 18 tLZWE tSD tHD
Note 18. During this period the I/Os are in the output state and input signals should not be applied.
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CY7C1011DV33
Truth Table
CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0-I/O7 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8-I/O15 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power-down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C1011DV33-10ZSXI CY7C1011DV33-10BVI CY7C1011DV33-10BVXI Package Diagram 51-85087 51-85150 Package Type 44-pin TSOP II (Pb-Free) 48-ball VFBGA 48-ball VFBGA (Pb-Free) Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts
Package Diagrams
Figure 1. 44-Pin TSOP II (51-85087)
51-85087-*A
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CY7C1011DV33
Package Diagrams (continued)
Figure 2. 48-Ball VFBGA (6 x 8 x 1 mm) (51-85150)
TOP VIEW
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B
A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C
51-85150-*D
SEATING PLANE 0.26 MAX. C 1.00 MAX
All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1011DV33
Document History
Document Title: CY7C1011DV33 2-Mbit (128K x 16)Static RAM Document Number: 38-05609 REV. ** *A ECN NO. 250650 399070 Issue Date See ECN See ECN Orig. of Change RKF NXR New Data Sheet Changed from Advance to Preliminary Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Removed TQFP Package from product offering Removed -15 speed bin Corrected DC voltage limits in maximum ratings section from -0.5 to -0.3V and VCC +0.5V to VCC +0.3V Redefined ICC values for Com'l and Ind'l temperature ranges ICC (Com'l): Changed from 100, 80 and 70 mA to 90, 80 and 75 mA for 8, 10 and 12ns speed bins respectively ICC (Ind'l): Changed from 80 and 70 mA to 90 and 85 mA for 10 and 12ns speed bins respectively Modified Note# 4 on AC Test Loads Added Static Discharge Voltage and latch-up current spec Added VIH(max) spec in Note# 2 Changed reference voltage level for measurement of Hi-Z parameters from 500 mV to 200 mV Added Data Retention Characteristics Table and footnote on tR Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram Changed package name for 44-pin TSOP II from Z to ZS Added 8 ns parts in the Ordering Information table Shaded Ordering Information Table Converted Preliminary to Final. Removed -8 and -12 Speed bins Removed Commercial Operating Range from product offering. Changed the description of IIX from "Input Load Current" to "Input Leakage Current" Updated the Thermal Resistance table. Changed tHZBE from 5 ns to 6 ns. Updated footnote #7 on High-Z parameter measurement Added footnote #12. Updated the Ordering Information and replaced Package Name column with Package Diagram in the Ordering Information table. Added -10BVI product ordering code in the Ordering Information table. Description of Change
*B
459073
See ECN
NXR
*C
480177
See ECN
VKN
Document #: 38-05609 Rev. *C
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